Ferroelectric(Fe)-NAND Flash Memory with Non-volatile Page Buffer for Data Center Application Enterprise Solid-State Drives (SSD)

被引：0

作者：

Hatanaka, Teruyoshi ^{[1
]}

Yajima, Ryoji ^{[1
]}

Horiuchi, Takeshi ^{[2
]}

Wang, Shouyu ^{[2
]}

Zhang, Xizhen ^{[2
]}

Takahashi, Mitsue ^{[2
]}

Sakai, Shigeki ^{[2
]}

Takeuchi, Ken ^{[1
]}

机构：

[1] Univ Tokyo, Informat Elect & Syst Engn Dept, Tokyo 1138654, Japan

[2] Natl Inst Adv Ind Sci & Technol, Tsukuba, Ibaraki 3058568, Japan

来源：

2009 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2009年

关键词：

SSD; NAND; Flash memory;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A ferroelectric(Fe)-NAND flash memory with a non-volatile (NV) page buffer is proposed. The data fragmentation in a random write is removed by introducing a batch write algorithm. As a result, the SSD performance can double. The NV-page buffer realizes a power outage immune highly reliable operation. With a low program/erase voltage, 6V and a high endurance, 100Million cycles, the proposed Fe-NAND is most suitable for a highly reliable high-speed low power data center application enterprise SSD.

引用

页码：78 / 79

页数：2

共 35 条

[1] Ferroelectric (Fe)-NAND Flash Memory With Batch Write Algorithm and Smart Data Store to the Nonvolatile Page Buffer for Data Center Application High-Speed and Highly Reliable Enterprise Solid-State Drives
Hatanaka, Teruyoshi
Yajima, Ryoji
Horiuchi, Takeshi
Wang, Shouyu
Zhang, Xizhen
Takahashi, Mitsue
Sakai, Shigeki
Takeuchi, Ken
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2010, 45 (10) : 2156 - 2164
[2] Storage Class Memory & NAND Flash Memory Hybrid Solid-State Drives (SSD)
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[3] Reliability of Solid-State Drives Based on NAND Flash Memory
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PROCEEDINGS OF THE IEEE, 2017, 105 (09) : 1725 - 1750
[4] Improvement of Read Disturb, Program Disturb and Data Retention by Memory Cell VTH Optimization of Ferroelectric (Fe)-NAND Flash Memories for Highly Reliable and Low Power Enterprise Solid-State Drives (SSDs)
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[7] Novel Co-Design of NAND Flash Memory and NAND Flash Controller Circuits for Sub-30 nm Low-Power High-Speed Solid-State Drives (SSD)
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[8] Novel co-design of NAND flash memory and NAND flash controller circuits for sub-30nm low-power high-speed Solid-State Drives (SSD)
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[9] Novel co-design of NAND flash memory and NAND flash controller circuits sub-30nm low-power high-speed Solid-State Drives (SSD)
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[10] Analyzing Power Management in Non-Volatile Memory Express (NVMe) Solid State Drives
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2019 IEEE PUNE SECTION INTERNATIONAL CONFERENCE (PUNECON), 2019,

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