Improving the cell characteristics using low-k gate Spacer in 1Gb NAND flash memory

被引：0
|
作者：
Kang, Daewoong [1 ]
Jang, Sungnam [1 ]
Lee, Kyongjoo [1 ]
Kim, Jinjoo [1 ]
Kwon, Hyukje [1 ]
Lee, Wonseong [1 ]
Park, Byung-Gook [1 ]
Lee, Jong Duk [1 ]
Shin, Hyungcheol [1 ]
机构：
[1] Seoul Natl Univ, Inter Univ Semicond Res Ctr, San 56-1 Shinlim Dong, Seoul 151742, South Korea
来源：
2006 INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2 | 2006年
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中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Floating gate interference resulting from capacitive coupling through parasitic capacitors surrounding the floating gate degrades the cell characteristics such as current, speed and cell V-th distribution. For the first time, we have introduced the cell characteristics improved using low-k dielectric of gate spacer such as oxide and air gap in 1 Gb NAND Flash memory.
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页码：744 / +
页数：2
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