An LOCV-based Static Timing Analysis Considering Spatial Correlations of Power Supply Variations

As the operating frequency of LSI becomes higher and the power supply voltage becomes lower, the on-chip power supply variation has become a dominant factor which influences the signal delay of the circuits. The static timing analysis (STA) considering on-chip power supply variations (IR-drop) is therefore one of the most crucial issues in the LSI designs nowadays. We propose an efficient STA method to consider on chip power supply variations in the static timing analysis by utilizing the spatial correlations of IR-drop. The proposed method is based on the widely-used technique in STA considering OCV (on-chip variations), which is called LOCV (Location-based OCV) technique, and therefore our method is easy to be incorporated into the existing timing analysis flow. The proposed method is evaluated by using test data including H-tree clock structure with various on-chip IR-drop distributions. The experimental results show that the proposed method can reduce the design margin with respect to power supply variations by 685% (47% on the average) compared with the conventional practical approach with a constant OCV derating factor, while requiring no additional computation cost in the static timing analysis. Thus the proposed method can contribute to a fast timing closure considering on-chip power supply variations.