Timing analysis considering spatial power/ground level variation

被引：0

作者：

Hashimoto, Masanori ^{[1
]}

Yamaguchi, Junji ^{[1
]}

Onodera, Hidetoshi ^{[1
]}

机构：

[1] Kyoto Univ, Dept Commun & Comp Engn, Kyoto 6068501, Japan

来源：

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES | 2007年 / E90A卷 / 12期

关键词：

timing analysis; power supply noise; gate delay model; power/ground level variation;

D O I：

10.1093/ietfec/e90-a.12.2661

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Spatial power/ground level variation causes power/ground level mismatch between driver and receiver, and the mismatch affects gate propagation delay. This paper proposes a timing analysis method based on a concept called "PG level equalization" which is compatible with conventional STA frameworks. We equalize the power/ground levels of driver and receiver. The charging/discharging current variation due to equalization is compensated by replacing output load. We present an implementation method of the proposed concept, and demonstrate that the proposed method works well for multiple-input gates and RC load model.

引用

页码：2661 / 2668

页数：8

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