Modeling temporal and spatial power supply voltage variation for timing analysis

This paper describes the full-chip power supply noise analysis methodology to accurately model the power supply voltage variation for signal integrity and timing analysis. An integrated chip and package power supply RLC model is developed to simultaneously analyze the resistive IR drop, inductive LDeltaI/Deltat noise, and capacitive decoupling on a full-chip scale. Steady-state noise due to maximum average current and transient noise due to power ramp-up, clock gating, and V-DD gating, are modeled with unit-based switching activities. Minimum V-DD, maximum V-DD, and average V-DD are calculated at each location on the chip, and used in timing analysis to provide a better range of V-DD variation than the standard 10% nominal V-DD noise budget. Time-dependent power supply voltage waveforms at various locations, based on a specific switching sequence, are also provided to simulate clock buffers and other timing-critical circuits under common-mode and differential-mode noise.