Efficient techniques for modeling chip-level interconnect, substrate and package parasitics

被引：0

作者：

Feldmann, P ^{[1
]}

Kapur, S ^{[1
]}

Long, DE ^{[1
]}

机构：

[1] AT&T Bell Labs, Lucent Technol, Naperville, IL 60566 USA

来源：

DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION 1999, PROCEEDINGS | 1999年

关键词：

D O I：

10.1109/DATE.1999.761158

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Modern IC design requires accurate analysis and modeling of chip-level interconnect the substrate and package parasitics. Traditional approaches for such analyses are computationally expensive. In this paper, we discuss some recent not el schemes for extraction and reduced order modeling that help overcome this computational bottleneck.

引用

页码：418 / 422

页数：5

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