共 50 条
- [1] Package and chip-level EMI/EMC structure design, modeling and simulation 49TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE - 1999 PROCEEDINGS, 1999, : 873 - 878
- [2] Application of chip-level EMC in automotive product design 2006 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY, VOLS 1-3, PROCEEDINGS, 2006, : 842 - 848
- [3] Efficient techniques for modeling chip-level interconnect, substrate and package parasitics DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION 1999, PROCEEDINGS, 1999, : 418 - 422
- [6] Chip-level ESD simulation for fail detection and design guidance 2004 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS, 2004, : 603 - 604
- [7] An unique method to fabricate on-chip capacitors for chip-level EMC evaluation PROCEEDINGS OF THE 2013 20TH IEEE INTERNATIONAL SYMPOSIUM ON THE PHYSICAL & FAILURE ANALYSIS OF INTEGRATED CIRCUITS (IPFA 2013), 2013, : 366 - 369
- [8] Design, simulation, fabrication, and characterization of package-level micro-shielding for EMI/EMC management in BGA environment 50TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE - 2000 PROCEEDINGS, 2000, : 793 - 798
- [9] Chip-Level CDM Circuit Modeling and Simulation for ESD Protection Design in 28nm CMOS 2018 14TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT), 2018, : 746 - 748
- [10] Implementation of Chip-Level EMC Strategies in 0.18 μm CMOS Technology 2017 ASIA-PACIFIC INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (APEMC), 2017, : 390 - 392