A Chip-Level Optical Interconnect for CPU

被引：3

作者：

Hao, Qinfen ^{[1
]}

Qin, Mengyuan ^{[1
]}

Qi, Nan ^{[2
]}

Xue, Haiyun ^{[3
]}

Han, Meng ^{[4
]}

Li, Xiaolin ^{[1
]}

Hao, Kai ^{[2
]}

Niu, Xingmao ^{[3
]}

Xiao, Limin ^{[4
]}

Fan, Dongrui ^{[1
]}

Kurata, Kazuhiko ^{[5
]}

机构：

[1] Chinese Acad Sci, Inst Comp Technol, Beijing 100190, Peoples R China

[2] Chinese Acad Sci, Inst Semicond, Beijing 100083, Peoples R China

[3] Chinese Acad Sci, Inst Microelect, Beijing 100029, Peoples R China

[4] Beihang Univ, Sch Comp Sci & Engn, Beijing 100191, Peoples R China

[5] AIO Core Co Ltd, Tokyo 1120014, Japan

来源：

IEEE PHOTONICS TECHNOLOGY LETTERS | 2021年 / 33卷 / 16期

关键词：

Integrated optics; Optical interconnections; Transceivers; Adaptive optics; Optical switches; Optical sensors; Power demand; digital integrated circuits; very high speed integrated circuits; chip scale packaging; system integration;

D O I：

10.1109/LPT.2021.3084945

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

With the rapid growth of electronic chip's performance, electric signal limits chip I/O in power consumption, reachability, and signal quality. In this letter, we propose a new chip-let architecture for chip-level optical interconnect. An optic I/O chip-let including an ultra-small optic transceiver and electronic components is implemented. Our analysis shows that the optical interconnect based on this architecture can achieve 1/3 power consumption and 1/2 area compared with traditional board-level optical interconnect in Ethernet NIC application. By adopting the architecture we proposed, the optic I/O chip-let can support any payload IC such as CPU, GPU, switch to have optic I/O.

引用

页码：852 / 855

页数：4

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