Partial rerouting algorithm for reconfigurable VLSI arrays

The problem of recon guring a two-dimensional degradable VLSI array under the row and column routing constraints has been shown to be NP-complete. This paper aims to decrease the recon guration time to enhance the real time application. A partial rerouting algorithm is proposed in this paper. For a given m x n VLSI array with the fault density rho, the proposed algorithm runs in O((1 - rho) (.) (tau) over bar (.) n) which is far less than O ((1 - rho) (.) m (.) n), the time complexity of the most ef cient algorithm, cited in the literature, where (tau) over bar is far less than m and it is nearly a constant for the small fault density. In addition, the proposed algorithm is exactly the same in harvest as the version reported so far.