Partial rerouting algorithm for reconfigurable VLSI arrays

被引：0

作者：

Wu, JG ^{[1
]}

Thambipillai, S ^{[1
]}

机构：

[1] Nanyang Technol Univ, Ctr High Performance Embedded Syst, Singapore 639798, Singapore

来源：

PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL V: BIO-MEDICAL CIRCUITS & SYSTEMS, VLSI SYSTEMS & APPLICATIONS, NEURAL NETWORKS & SYSTEMS | 2003年

关键词：

VLSI/WSI array; recon gurable system; fault-tolerance; algorithm design; NP-completeness;

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

The problem of recon guring a two-dimensional degradable VLSI array under the row and column routing constraints has been shown to be NP-complete. This paper aims to decrease the recon guration time to enhance the real time application. A partial rerouting algorithm is proposed in this paper. For a given m x n VLSI array with the fault density rho, the proposed algorithm runs in O((1 - rho) (.) (tau) over bar (.) n) which is far less than O ((1 - rho) (.) m (.) n), the time complexity of the most ef cient algorithm, cited in the literature, where (tau) over bar is far less than m and it is nearly a constant for the small fault density. In addition, the proposed algorithm is exactly the same in harvest as the version reported so far.

引用

页码：641 / 644

页数：4

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