A low power algorithm for reconfigurable VLSI/WSI arrays

被引：0
|
作者：
Wu, JA [1 ]
Srikanthan, T [1 ]
Patel, CR [1 ]
机构：
[1] Nanyang Technol Univ, Ctr High Performance Embedded Syst, Singapore 639798, Singapore
来源：
ESA'03: PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS AND APPLICATIONS | 2003年
关键词：
degradable VLSI/WSI array; reconfiguration; heuristic algorithm fault-tolerance; NP-completeness;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Given an m x n mesh-connected VLSL/WSI array with some faulty elements, the reconfiguration problem is to find a maximum-sized fault-free sub-array under the row and column rerouting scheme. This problem has already been shown to be NP-complete. The power awareness problem of the reconfigurable VLSI/WSI array is first proposed in this paper A heuristic algorithm has been presented for the same. The performance of the proposed algorithm is more powerful than that of the older algorithm, without loss of harvest.
引用
收藏
页码：237 / 242
页数：6
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