Optimization of 3D Stacked Nanosheets in 5nm Gate-all-around Transistor Technology

被引：1
|
作者：
Gundu, Anil Kumar [1 ]
Kursun, Volkan [2 ]
机构：
[1] Hong Kong Univ Sci & Technol, Dept Elect & Comp Engn, Kowloon, Clear Water Bay, Hong Kong, Peoples R China
[2] Norwegian Univ Sci & Technol, Dept Elect Syst, N-7034 Trondheim, Norway
来源：
34TH IEEE INTERNATIONAL SYSTEM ON CHIP CONFERENCE (SOCC) | 2021年
关键词：
Gate-all-around; stacked nanosheet; footprint; short-channel effect; minimum sized inverter;
D O I：
10.1109/SOCC52499.2021.9739517
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
An optimization study of silicon gate-all-around (GAA) devices based on technology computer-aided design tools is presented in this paper. GAA technology guidelines and solutions are provided for low power applications in the 5 nm CMOS technology node. GAA device structure is optimized to achieve maximum electrostatics driven performance. Vertically stacked lateral nanosheet devices display superior performance and area scaling as compared to the conventional finFET and GAA technologies. Gate-all-around nanosheet (NS) devices with sheet width of 8nm enhance the performance of a CMOS inverter by 18.67% while reducing the area by 14.54% as compared to the finFETs with horizontal device footprints of 25nm.
引用
收藏
页码：25 / 28
页数：4
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