DICE: A beneficial short-channel effect in nanoscale double-gate MOSFETs

被引：1
|
作者：
Chouksey, Siddharth [1 ]
Fossum, Jerry G. [1 ]
机构：
[1] Univ Florida, Dept Elect & Comp Engn, Gainesville, FL 32611 USA
来源：
IEEE TRANSACTIONS ON ELECTRON DEVICES | 2008年 / 55卷 / 03期
关键词：
drain-induced barrier lowering (DIBL); FinFET physical compact model; short-channel effects; velocity overshoot;
D O I：
10.1109/TED.2007.914835
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Physics-based compact modeling, supported by numerical simulations, is used to show the significance of "drain-induced charge enhancement" (DICE) in nanoscale double-gate (DG) MOSFETs. DICE, which is the strong-inversion counterpart of drain-induced barrier lowering (DIBL), is shown to significantly benefit drive current, without affecting the gate capacitance much, and hence can improve nanoscale DG CMOS speed substantially.
引用
收藏
页码：796 / 802
页数：7
相关论文
共 50 条
  • [31] Numerical Simulation of Nanoscale Double-Gate MOSFETs
    Stenzel, R.
    Mueller, L.
    Herrmann, T.
    Klix, W.
    ACTA POLYTECHNICA, 2006, 46 (05) : 35 - 39
  • [32] A Quasi-2D Threshold Voltage Model for Short-channel Junctionless (JL) Double-gate MOSFETs
    Chiang, Te-Kuang
    2012 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID STATE CIRCUIT (EDSSC), 2012,
  • [33] Short-Channel Double-Gate FETs with Atomically Precise Graphene Nanoribbons
    Mutlu, Z.
    Lin, Y.
    Barin, G. B.
    Zhang, Z.
    Pitner, G.
    Wang, S.
    Darawish, R.
    Di Giovannantonio, M.
    Wang, H.
    Cai, J.
    Passlack, M.
    Diaz, C. H.
    Narita, A.
    Muellen, K.
    Fischer, F. R.
    Bandaru, P.
    Kummel, A. C.
    Ruffieux, P.
    Fasel, R.
    Bokor, J.
    2021 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2021,
  • [34] Unified Charge Model for Short-Channel Junctionless Double Gate MOSFETs
    Holtij, Thomas
    Graef, Michael
    Hain, Franziska
    Kloes, Alexander
    Iniguez, Benjamin
    MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, MIXDES 2013, 2013, : 75 - 80
  • [35] Double-gate junctionless transistor model including short-channel effects
    Paz, B. C.
    Avila-Herrera, F.
    Cerdeira, A.
    Pavanello, M. A.
    SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2015, 30 (05) : 1 - 11
  • [36] Compact model for short-channel symmetric double-gate junctionless transistors
    Avila-Herrera, F.
    Cerdeira, A.
    Paz, B. C.
    Estrada, M.
    Iniguez, B.
    Pavanello, M. A.
    SOLID-STATE ELECTRONICS, 2015, 111 : 196 - 203
  • [37] Compact model for short channel symmetric doped double-gate MOSFETs
    Cerdeira, Antonio
    Iniguez, Benjamin
    Estrada, Magali
    SOLID-STATE ELECTRONICS, 2008, 52 (07) : 1064 - 1070
  • [38] Double jeopardy in the nanoscale court? Modeling the scaling limits of double-gate MOSFETs with physics-based compact short-channel models of threshold voltage and subthreshold swing
    Chen, Q
    Bowman, KA
    Harrell, EM
    Meindl, JD
    IEEE CIRCUITS & DEVICES, 2003, 19 (01): : 28 - 34
  • [39] Drain current model for nanoscale double-gate MOSFETs
    Hariharan, Venkatnarayan
    Thakker, Rajesh
    Singh, Karmvir
    Sachid, Angada B.
    Patil, M. B.
    Vasi, Juzer
    Rao, V. Ramgopal
    SOLID-STATE ELECTRONICS, 2009, 53 (09) : 1001 - 1008
  • [40] A subthreshold current model for nanoscale short channel junctionless MOSFETs applicable to symmetric and asymmetric double-gate structure
    Jin, Xiaoshi
    Liu, Xi
    Kwon, Hyuck-In
    Lee, Jung-Hee
    Lee, Jong-Ho
    SOLID-STATE ELECTRONICS, 2013, 82 : 77 - 81
12345