Physics-based compact modeling, supported by numerical simulations, is used to show the significance of "drain-induced charge enhancement" (DICE) in nanoscale double-gate (DG) MOSFETs. DICE, which is the strong-inversion counterpart of drain-induced barrier lowering (DIBL), is shown to significantly benefit drive current, without affecting the gate capacitance much, and hence can improve nanoscale DG CMOS speed substantially.
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School of Information Science and Engineering,Shenyang University of TechnologySchool of Information Science and Engineering,Shenyang University of Technology
吴美乐
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揣荣岩
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Jung-Hee Lee
Jong-Ho Lee
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School of EECS Eng.and ISRC(Inter-University Semiconductor Research Center),Seoul National UniversitySchool of Information Science and Engineering,Shenyang University of Technology
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Shenyang Univ Technol, Sch Informat Sci & Engn, Shenyang, Liaoning 110870, Peoples R ChinaShenyang Univ Technol, Sch Informat Sci & Engn, Shenyang, Liaoning 110870, Peoples R China
Jin Xiaoshi
Liu Xi
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Shenyang Univ Technol, Sch Informat Sci & Engn, Shenyang, Liaoning 110870, Peoples R ChinaShenyang Univ Technol, Sch Informat Sci & Engn, Shenyang, Liaoning 110870, Peoples R China
Liu Xi
Wu Meile
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Shenyang Univ Technol, Sch Informat Sci & Engn, Shenyang, Liaoning 110870, Peoples R ChinaShenyang Univ Technol, Sch Informat Sci & Engn, Shenyang, Liaoning 110870, Peoples R China
Wu Meile
Chuai Rongyan
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Shenyang Univ Technol, Sch Informat Sci & Engn, Shenyang, Liaoning 110870, Peoples R ChinaShenyang Univ Technol, Sch Informat Sci & Engn, Shenyang, Liaoning 110870, Peoples R China
Chuai Rongyan
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Jung-Hee Lee
Jong-Ho Lee
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Seoul Natl Univ, Inter Univ Semicond Res Center, Sch EECS, Seoul 151742, South KoreaShenyang Univ Technol, Sch Informat Sci & Engn, Shenyang, Liaoning 110870, Peoples R China