Evolutionary computation engine for floor-planning

被引:0
|
作者
Yoshikawa, M [1 ]
Terai, H [1 ]
机构
[1] Ritsumeikan Univ, Coll Sci & Engn, Shiga 5258577, Japan
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper discusses the architecture for high speed floor-planning using sequence pair representation based on Genetic Algorithms (GA). The proposed architecture, which is called ECE (Evolutionary Computation Engine), prevents local minimum by using the GA characteristic of holding several individual populations for a population-based search and achieves high speed processing by adopting dedicated hardware. To keep general purpose, the proposed architecture is flexible for many genetic operations on GA. The proposed architecture is implemented on FPGA. Measurement results evaluating the proposed architecture are shown to achieve speeds 375 times greater than software processing.
引用
收藏
页码:267 / 271
页数:5
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