Reallocation and rescheduling after floor-planning for timing optimization

As the dimension of integrated circuits proceeds into deep sub-micron level, interconnect delay is playing a dominant role in total delay of a circuit. The result of high-level synthesis is often violated by interconnect-delay in physical design phase, especially in timing aspect. Reallocation and Rescheduling after floor-plan can be very helpful to the delay optimization of physical design. A force-balance based interconnect-delay driven algorithm for reallocation and rescheduling (FIDER) is presented in this paper. The delay of interconnect wire is specially attended in this algorithm. In this algorithm, a reallocation process is first engaged after floor-planning, in order to erase those data-paths which do not satisfy the timing constraint. A rescheduling process will be engaged if this reallocation process is not successfully finished. A HLS system, TUSYN, is also presented as the background knowledge of the algorithm.