Optimization of Floor-planning using Genetic Algorithm

Floor-planning is one of the key design flow of VLSI chip designing process. This paper presents a novel approach to solve the VLSI floor planning problems. This approach is based on iterative prototypes optimization with evolved improvement (POEMS) algorithm. It uses a genetic algorithm (GA) for local search on each iteration, because both algorithms have already proven useful for solving similar problems. It adopts a non-slicing structure B* tree for the placement of rectangle modules. B*-trees are based on ordered binary trees. Inheriting from the nice properties of ordered binary trees, B*-trees are very easy for implementation and can perform the respective primitive tree operations, like search, insertion, and deletion in only O(1), O(1) and O(n) times respectively. While existing representations for non-slicing floor-plans need at least O(n) time for each of these operations, where n is the number of modules. GA has been implemented and tested on popular benchmark problems. Experimental results show that GA can quickly produce optimal solutions for all tested benchmark problems. (C) 2011 Published by Elsevier Ltd. Selection and/or peer-review under responsibility of C3IT