Fast physics based wafer-level reliability characterisation

被引：0
|
作者：
Krozer, V [1 ]
Schüssler, M [1 ]
Ganis, H [1 ]
Brandt, M [1 ]
Sydlo, C [1 ]
Mottet, B [1 ]
Cassette, S [1 ]
Delage, S [1 ]
Hartnagel, HL [1 ]
机构：
[1] TU Chemnitz, D-09126 Chemnitz, Germany
来源：
2000 IEEE INTERNATIONAL INTEGRATED RELIABILITY WORKSHOP FINAL REPORT | 2000年
关键词：
D O I：
10.1109/IRWS.2000.911932
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A fast method for reliability evaluation and wafer level reliability measurements is presented. This method requires a physics-of-failure based approach. We propose pulsed electrical stress for reliability and thermal characterisation and present both experimental and theoretical results. An improved measurement set-up allows dynamic pulse-response measurement and direct parameter extraction. Dedicated analytical and numerical physical models have been developed. Step stress tests were carried out on HBT, Schottky diode and TLM structures. An extraction of electric field, internal temperature, carrier distribution and charge carrier temperature was performed, based on physical device models. Different device degradation mechanisms are analyzed and their relevance is discussed with respect to life-time calculation.
引用
收藏
页码：171 / 174
页数：4
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