Fast physics based wafer-level reliability characterisation

被引：0
|
作者：
Krozer, V [1 ]
Schüssler, M [1 ]
Ganis, H [1 ]
Brandt, M [1 ]
Sydlo, C [1 ]
Mottet, B [1 ]
Cassette, S [1 ]
Delage, S [1 ]
Hartnagel, HL [1 ]
机构：
[1] TU Chemnitz, D-09126 Chemnitz, Germany
来源：
2000 IEEE INTERNATIONAL INTEGRATED RELIABILITY WORKSHOP FINAL REPORT | 2000年
关键词：
D O I：
10.1109/IRWS.2000.911932
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A fast method for reliability evaluation and wafer level reliability measurements is presented. This method requires a physics-of-failure based approach. We propose pulsed electrical stress for reliability and thermal characterisation and present both experimental and theoretical results. An improved measurement set-up allows dynamic pulse-response measurement and direct parameter extraction. Dedicated analytical and numerical physical models have been developed. Step stress tests were carried out on HBT, Schottky diode and TLM structures. An extraction of electric field, internal temperature, carrier distribution and charge carrier temperature was performed, based on physical device models. Different device degradation mechanisms are analyzed and their relevance is discussed with respect to life-time calculation.
引用
收藏
页码：171 / 174
页数：4
相关论文
共 50 条
  • [31] Wafer-Level Assembly of Physics Package for Chip-Scale Atomic Clocks
    Guo, Ping
    Meng, Hongling
    Dan, Lin
    Zhao, Jianye
    [J]. IEEE SENSORS JOURNAL, 2022, 22 (07) : 6387 - 6398
  • [32] Wafer-level packaging update
    Demmin, JC
    [J]. SOLID STATE TECHNOLOGY, 2003, 46 (11) : 34 - +
  • [33] Electromigration Reliability of Redistribution Lines in Wafer-level Chip-Scale Packages
    Lai, Yi-Shao
    Kao, Chin-Li
    Chiu, Ying-Ta
    Appelt, Bernd K.
    [J]. 2011 IEEE 61ST ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2011, : 326 - 331
  • [34] Reliability hazard characterization of wafer-level spatial metrology parameters based on LOF-KNN method
    Zhang, Jinli
    You, Hailong
    Jia, Renxu
    [J]. 2019 IEEE 26TH INTERNATIONAL SYMPOSIUM ON PHYSICAL AND FAILURE ANALYSIS OF INTEGRATED CIRCUITS (IPFA), 2019,
  • [35] Isothermal wafer-level electromigration test for the characterization of metal system reliability monitoring
    Kuo, CY
    Yuan, HC
    Lee, SC
    Lee, SY
    Chu, LH
    Shiue, RY
    Yue, JT
    [J]. 2001 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS, PROCEEDINGS OF TECHNICAL PAPERS, 2001, : 275 - 278
  • [36] Wafer-level reliability assessment of SiGeNPNHBTs after high temperature electrical operation
    Hofmann, K
    Bruegmann, G
    Lill, A
    [J]. 2002 IEEE INTERNATIONAL INTEGRATED RELIABILITY WORKSHOP - FINAL REPORT, 2002, : 79 - 82
  • [37] Improvement of Thermo-Mechanical Reliability of Wafer-Level Chip Scale Packaging
    Shi, Lei
    Chen, Lin
    Zhang, David Wei
    Liu, Evan
    Liu, Qiang
    Chen, Ching-I
    [J]. JOURNAL OF ELECTRONIC PACKAGING, 2018, 140 (01)
  • [38] Wafer-level electromigration reliability test for deep-submicron interconnect metallization
    Loh, WB
    Tse, MS
    Chan, L
    Lo, KF
    [J]. 1998 IEEE HONG KONG ELECTRON DEVICES MEETING, PROCEEDINGS, 1998, : 157 - 160
  • [39] Reliability statistics perspective on standard wafer-level electromigration accelerated test (SWEAT)
    Tan, CM
    Yeo, KNC
    [J]. 2000 CANADIAN CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING, CONFERENCE PROCEEDINGS, VOLS 1 AND 2: NAVIGATING TO A NEW ERA, 2000, : 167 - 172
  • [40] Assembly and reliability assessment of lithography-based wafer-level compliant chip-to-substrate interconnects
    Kacker, K
    Lo, G
    Sitaraman, SK
    [J]. 55TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, VOLS 1 AND 2, 2005 PROCEEDINGS, 2005, : 545 - 550
12345