Fast, wafer-level detection and control of interconnect reliability

被引:0
|
作者
Foley, S [1 ]
Molyneaux, J [1 ]
Mathewson, A [1 ]
机构
[1] Natl Univ Ireland Univ Coll Cork, Natl Microelect Res Ctr, Cork, Ireland
来源
关键词
electromigration; Stress-voids; interconnect; reliability; wafer-level; detection; control;
D O I
10.1117/12.410075
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
Many of the technological advances in the semiconductor industry have led to dramatic increases in device density and performance in conjunction with enhanced circuit reliability. As reliability is improved, the time taken to characterise particular failure modes with traditional test methods is getting substantially longer. Furthermore, semiconductor customers expect low product cost and fast time-to-market. The limits of traditional reliability testing philosophies are being reached and new approaches need to be investigated to enable the next generation of highly reliable products to be tested. This is especially true in the area of IC interconnect, where significant challenges are predicted for the next decade. A number of fast, wafer level test methods exist for interconnect reliability evaluation. The relative abilities of four such methods to detect the quality and reliability of IC interconnect over very short test times are evaluated in this work. Four different test structure designs are also evaluated and the results are bench-marked against conventional package level Median Time to Failure (MTF) results. The Isothermal test method combined with SWEAT-type test structures is shown to be the most suitable combination for defect detection and interconnect reliability control over very short test times.
引用
收藏
页码:166 / 177
页数:12
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