Gate-All-Around Junctionless Transistors With Heavily Doped Polysilicon Nanowire Channels

被引：153

作者：

Su, Chun-Jung ^{[1
]}

Tsai, Tzu-I ^{[2
]}

Liou, Yu-Ling ^{[3
,4
]}

Lin, Zer-Ming ^{[3
,4
]}

Lin, Horng-Chih ^{[3
,4
]}

Chao, Tien-Sheng ^{[2
]}

机构：

[1] Natl Chiao Tung Univ, Nano Facil Ctr, Hsinchu 300, Taiwan

[2] Natl Chiao Tung Univ, Dept Electrophys, Hsinchu 300, Taiwan

[3] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu 300, Taiwan

[4] Natl Chiao Tung Univ, Inst Elect, Hsinchu 300, Taiwan

来源：

IEEE ELECTRON DEVICE LETTERS | 2011年 / 32卷 / 04期

关键词：

Accumulation mode; gate all around (GAA); inversion mode (IM); nanowire (NW); thin-film transistor (TFT); THIN-FILM TRANSISTORS; LENGTH;

D O I：

10.1109/LED.2011.2107498

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this letter, we have investigated experimentally, for the first time, the feasibility of gate-all-around polycrystalline silicon (poly-Si) nanowire transistors with junctionless (JL) configuration by utilizing only one heavily doped poly-Si layer to serve as source, channel, and drain regions. In situ doped poly-Si material features high and uniform-doping concentration, facilitating the fabrication process. The developed JL device exhibits desirable electrostatic performance in terms of higher ON/OFF current ratio and lower source/drain series resistance as compared with the inversion-mode counterpart. Such scheme appears of great potential for future system-on-panel and 3-D IC applications.

引用

页码：521 / 523

页数：3

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