Modeling and analysis of total leakage currents in nanoscale Double Gate devices and circuits

被引：0

作者：

Mukhopadhyay, S ^{[1
]}

Kim, K ^{[1
]}

Chuang, CT ^{[1
]}

Roy, K ^{[1
]}

机构：

[1] Purdue Univ, Dept ECE, W Lafayette, IN 47907 USA

来源：

ISLPED '05: PROCEEDINGS OF THE 2005 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN | 2005年

关键词：

Double-Gate devices; Gate leakage; subthreshold leakage; quantum effect; stacking effect; SRAM;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper we model (numerically and analytically) and analyze sub-threshold, gate-to-channel tunneling, and edge direct tunneling leakage in Double Gate (DG) devices. We compare the leakage of different DG structures, namely, doped body symmetric device with polysilicon gates, intrinsic body symmetric device with metal gates and intrinsic body asymmetric device with different front and back gate material. It is observed that, use of (near-midgap) metal gate and intrinsic body devices significantly reduces both the total leakage and its sensitivity to parametric variations in DG circuits.

引用

页码：8 / 13

页数：6

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