Impact of Process Variations on Negative Capacitance FinFET Devices and Circuits

被引:44
|
作者
Dutta, Tapas [1 ]
Pahwa, Girish [1 ]
Agarwal, Amit [2 ]
Chauhan, Yogesh Singh [1 ]
机构
[1] IIT Kanpur, NanoLab, Dept Elect Engn, Kanpur 208016, Uttar Pradesh, India
[2] Indian Inst Technol, Dept Phys, Kanpur 208016, Uttar Pradesh, India
关键词
Negative capacitance; FinFET; ferroelectric; process variation; 7 nm technology node; Monte-Carlo simulations; VOLTAGE AMPLIFICATION;
D O I
10.1109/LED.2017.2770158
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We report on the impact of process variations on short-channel negative capacitance (NC)-based FinFETs through statistical Monte Carlo simulations using a physics-based model of NC-FinFETs. We find that relative to regular FinFETs, the impact of geometrical variability can be lesser or higher in NC-FinFETs in different regimes of device operation and is strongly dependent on the nominal ferroelectric (FE) thickness (t(fe)). The contribution of the FE layer to the overall variability behaves non-monotonically with increase in the nominal tfe. While the OFF-current and threshold voltage variabilities scale down, the ON-current variability does not follow a monotonic trend with increase in the nominal t(fe). We also show that although relative to the regular FinFET-based ring oscillator (RO) circuit, the NC-FinFET-based RO (NC-RO) circuit displays increased immunity to process variation induced delay variability, the trend is non-monotonic with regard to tfe scaling.
引用
收藏
页码:147 / 150
页数:4
相关论文
共 50 条
  • [1] Impact of Radiation on Negative Capacitance FinFET
    Bajpai, Govind
    Gupta, Aniket
    Prakash, Om
    Pahwa, Girish
    Henkel, Joerg
    Chauhan, Yogesh S.
    Amrouch, Hussam
    [J]. 2020 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2020,
  • [2] Negative Capacitance Circuits for Process Variations Compensation and Timing Yield Improvement
    Mostafa, Hassan
    Anis, Mohab
    Elmasry, Mohamed
    [J]. 2014 IEEE 27TH CANADIAN CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING (CCECE), 2014,
  • [3] Negative Capacitance Circuits for Process Variations Compensation and Timing Yield Improvement
    Mostafa, Hassan
    Anis, Mohab
    Elmasry, Mohamed
    [J]. 2013 IEEE 20TH INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS, AND SYSTEMS (ICECS), 2013, : 277 - 280
  • [4] Impact of Parasitic Capacitance and Ferroelectric Parameters on Negative Capacitance FinFET Characteristics
    Khandelwal, Sourabh
    Duarte, Juan Pablo
    Khan, Asif Islam
    Salahuddin, Sayeef
    Hu, Chenming
    [J]. IEEE ELECTRON DEVICE LETTERS, 2017, 38 (01) : 142 - 144
  • [5] VDD scaling for FinFET logic and memory circuits:: the impact of process variations and SRAM stability
    Lin, C. -H.
    Das, K. K.
    Chang, L.
    Williams, R. Q.
    Haensch, W. E.
    Hu, C.
    [J]. 2006 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS (VLSI-TSA), PROCEEDINGS OF TECHNICAL PAPERS, 2006, : 38 - +
  • [6] Impact of Variability on Processor Performance in Negative Capacitance FinFET Technology
    Amrouch, Hussam
    Pahwa, Girish
    Gaidhane, Amol D.
    Dabhi, Chetan K.
    Klemme, Florian
    Prakash, Om
    Chauhan, Yogesh Singh
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2020, 67 (09) : 3127 - 3137
  • [7] The Effects of Process Variations and BTI in Packaged FinFET Devices
    Bender, E.
    Bernstein, J. B.
    Boning, D. S.
    [J]. 2023 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, IRPS, 2023,
  • [8] Impact of Interface Traps Induced Degradation on Negative Capacitance FinFET
    Prakash, Om
    Gupta, Aniket
    Pahwa, Girish
    Henkel, Joerg
    Chauhan, Yogesh S.
    Amrouch, Hussam
    [J]. 2020 IEEE ELECTRON DEVICES TECHNOLOGY AND MANUFACTURING CONFERENCE (EDTM 2020), 2020,
  • [9] Impact of Process-Induced Variations on Negative Capacitance Junctionless Nanowire FET
    Choi, Yejoo
    Lee, Jinwoong
    Lim, Jaehyuk
    Moon, Seungjun
    Shin, Changhwan
    [J]. ELECTRONICS, 2021, 10 (16)
  • [10] Sensitivity of double-gate and FinFET devices to process variations
    Xiong, SY
    Bokor, J
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2003, 50 (11) : 2255 - 2261