共 50 条
- [41] Die Level 3D Heterogeneous Integration of a Microfluidic System [J]. 2017 IEEE 19TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC), 2017,
- [43] An innovative die to wafer 3D integration scheme : Die to wafer oxide or copper direct bonding with planarised oxide inter-die filling. [J]. 2009 IEEE INTERNATIONAL CONFERENCE ON 3D SYSTEMS INTEGRATION, 2009, : 380 - +
- [44] Research of Electroplating and Electroless Plating for Low Temperature Bonding in 3D Heterogeneous Integration [J]. 2014 9TH INTERNATIONAL MICROSYSTEMS, PACKAGING, ASSEMBLY AND CIRCUITS TECHNOLOGY CONFERENCE (IMPACT), 2014, : 290 - 293
- [45] Dielectric glue wafer bonding and bonded wafer thinning for wafer-level 3D integration [J]. SEMICONDUCTOR WAFER BONDING VII: SCIENCE, TECHNOLOGY, AND APPLICATIONS, PROCEEDINGS, 2003, 2003 (19): : 76 - 86
- [46] Plasma Activation as a Pretreatment Tool for Low-Temperature Direct Wafer Bonding in Microsystems Technology [J]. SEMICONDUCTOR WAFER BONDING 12: SCIENCE, TECHNOLOGY, AND APPLICATIONS, 2012, 50 (07): : 265 - 276
- [47] A Novel Die to Wafer (D2W) Collective Bonding Method for MEMS and Electronics Heterogeneous 3D Integration [J]. 2010 PROCEEDINGS 60TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2010, : 829 - 833
- [49] Low temperature bonding technology for 3D integration [J]. MICROELECTRONICS RELIABILITY, 2012, 52 (02) : 302 - 311