A 32 kb Macro with 8T Soft Error Robust, SRAM Cell in 65-nm CMOS

被引：25

作者：

Shah, Jaspal Singh ^{[1
]}

Nairn, David ^{[2
]}

Sachdev, Manoj ^{[2
]}

机构：

[1] Univ Waterloo, Waterloo, ON N2L 3G1, Canada

[2] Univ Waterloo, Dept Elect & Comp Engn, Waterloo, ON N2L 3G1, Canada

来源：

IEEE TRANSACTIONS ON NUCLEAR SCIENCE | 2015年 / 62卷 / 03期

关键词：

Hardened by design (HBD); single-event upset (SEU); soft-error rate (SER); soft-error robust; SRAM; DESIGN; UPSETS;

D O I：

10.1109/TNS.2015.2429589

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 32-kb macro containing an eight-transistor soft error robust SRAM cell with differential read and write capabilities is presented. The 8T cell does not have dedicated access transistors, and its quad-latch configuration stores data on four interlocked storage nodes. The macro was designed in a 65-nm CMOS process. The cell demonstrates excellent read data stability down to 0.55 V and is well suited for low-voltage, low-power applications. Neutron radiation testing on the macro exhibits at least 15x improvement in Failure in Time (FIT) rate compared with the conventional 6T SRAM cell in 65-nm CMOS technology.

引用

页码：1367 / 1374

页数：8

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