Low-temperature transport characteristics and quantum-confinement effects in gate-all-around Si-nanowire N-MOSFET

被引：33

作者：

Rustagi, Subhash C. ^{[1
]}

Singh, N. ^{[1
]}

Lim, Y. F. ^{[1
]}

Zhang, G. ^{[1
]}

Wang, S. ^{[1
]}

Lo, G. Q. ^{[1
]}

Balasubramanian, N. ^{[1
]}

Kwong, D.-L. ^{[1
]}

机构：

[1] Inst Microelect, Singapore 117865, Singapore

来源：

IEEE ELECTRON DEVICE LETTERS | 2007年 / 28卷 / 10期

关键词：

carrier transport; gate all around; low temperature; MOSFET; silicon nanowire (SiNW);

D O I：

10.1109/LED.2007.904890

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Gate-all-around n-MOSFETs with Si-nanowire (similar to 7 nm) as the channel body are fabricated and characterized for their low-temperature behavior (similar to 5 K to 295 K). I-DS-V-GS characteristics at low V-DS (similar to 50 mV) exhibit a decrease in current with decreasing temperature in strong inversion up to about similar to 200 K. However, at high V-DS, drain current reverts to typical temperature behavior, i.e., I-DS increases with the reducing temperature due to the increase in phonon-limited mobility (mu(ph)). It is inferred that, at low VDS, the enhancement in mu(ph) at a reduced temperature could be possibly masked by the intersubband scattering on account of subband splitting due to quantum-confinement effects as indicated by subband calculations for nanowire structures.

引用

页码：909 / 912

页数：4

共 50 条

[1] Gate-All-Around Si-Nanowire Transistors: Simulation at Nanoscale
Dey, S.
Dash, T. P.
Das, S.
Mohapatra, E.
Jena, J.
Maiti, C. K.
[J]. PROCEEDINGS OF 2018 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES KOLKATA CONFERENCE (IEEE EDKCON), 2018, : 137 - 141
[2] Si-nanowire based gate-all-around nonvolatile SONOS memory cell
Fu, J.
Singh, N.
Buddharaju, K. D.
Teo, S. H. G.
Shen, C.
Jiang, Y.
Zhu, C. X.
Yu, M. B.
Lo, G. Q.
Balasubramanian, N.
Kwong, D. L.
Gnani, E.
Baccarani, G.
[J]. IEEE ELECTRON DEVICE LETTERS, 2008, 29 (05) : 518 - 521
[3] Atomistic modeling of gate-all-around Si-nanowire field-effect transistors
Pecchia, Alessandro
Salamandra, Luigi
Latessa, Luca
Aradi, Balint
Frauenheim, Thomas
Di Carlo, Aldo
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007, 54 (12) : 3159 - 3167
[4] Quantum Transport Simulations of the Zero Temperature Coefficient in Gate-all-around Nanowire pFETs
Lee, Hyeongu
Seo, Junbeom
Shin, Mincheol
[J]. 2019 INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES (SISPAD 2019), 2019, : 117 - 120
[5] Field Stress Influenced Conduction Behavior of Narrow Diameter Gate-All-Around (GAA) Silicon Nanowire n-MOSFET
Deepak K. Sharma
Ranjith Kumar Goud
Arnab Datta
Sanjeev Manhas
[J]. Journal of Electronic Materials, 2019, 48 : 7674 - 7679
[6] Subthreshold Swing in Silicon Gate-All-Around Nanowire MOSFET at Cryogenic Temperature
Sekiguchi, Shohei
Ahn, Min-Ju
Saraya, Takuya
Kobayashi, Masaharu
Hiramoto, Toshiro
[J]. 2021 5TH IEEE ELECTRON DEVICES TECHNOLOGY & MANUFACTURING CONFERENCE (EDTM), 2021,
[7] Field Stress Influenced Conduction Behavior of Narrow Diameter Gate-All-Around (GAA) Silicon Nanowire n-MOSFET
Sharma, Deepak K.
Goud, Ranjith Kumar
Datta, Arnab
Manhas, Sanjeev
[J]. JOURNAL OF ELECTRONIC MATERIALS, 2019, 48 (12) : 7674 - 7679
[8] Compact modelling for quantum confinement for InGaAs nanowire gate all around MOSFET
Abdelmoneam, A.
Iniguez, B.
[J]. ELECTRONICS LETTERS, 2018, 54 (23) : 1348 - 1349
[9] Random Dopant Fluctuation Induced Variability in Undoped Channel Si Gate All Around Nanowire n-MOSFET
Nayak, Kaushik
Agarwal, Samarth
Bajaj, Mohit
Murali, Kota V. R. M.
Rao, Valipe Ramgopal
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2015, 62 (02) : 685 - 688
[10] On quantum effects and low frequency noise spectroscopy in Si Gate-All-Around Nanowire MOSFETs at cryogenic temperatures
Boudier, D.
Cretu, B.
Simoen, E.
Veloso, A.
Collaert, N.
[J]. 2017 JOINT INTERNATIONAL EUROSOI WORKSHOP AND INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON (EUROSOI-ULIS 2017), 2017, : 5 - 8

← 1 2 3 4 5 →