High Speed Low Power Dual-Edge Triggered D flip-flop

被引：0

作者：

Shandilya, Rahul ^{[1
]}

Sharma, Rk ^{[1
]}

机构：

[1] Natl Inst Technol Kurukshetra, Sch VLSI Design & Embedded Syst, Kurukshetra, Haryana, India

来源：

PROCEEDINGS OF 2017 INTERNATIONAL CONFERENCE ON INTELLIGENT COMPUTING AND CONTROL (I2C2) | 2017年

关键词：

Flip-Flop (FF); low powered; Pulse triggered; PDP;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, a low power and high speed dual-edge triggered D flip-flop has been presented. The proposed design reduces the power dissipation and improves the delay. So the overall power-delay product is improved. The power dissipation observed is 17.5 mu W and delay observed is 91psec. The PDP is 1.59fJ which outperforms the designs reported in literature. The simulation results has been carried out in Cadence Virtuoso Analog Design Environment in UMC.18 mu m technology. The proposed design has been compared on different frequencies and voltages.

引用

页数：5

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