A low-voltage, low-power, high-linearity CMOS four-quadrant analog multiplier

被引：12
|
作者：
Sawigun, Chutham [1 ]
Demosthenous, Andreas [2 ]
Pal, Dipankar [2 ]
机构：
[1] Mahanakom Univ Technol, Dept Elect Engn, Bangkok, Thailand
[2] UCL, Dept Elect & Elect Engn, Torrington Pl, London WC1E 7JE, England
来源：
2007 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOLS 1-3 | 2007年
关键词：
D O I：
10.1109/ECCTD.2007.4529705
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A compact four-quadrant analog multiplier circuit using strong inversion saturated MOSFETs is presented. The circuit is formed by connecting simple 2-input "combiner" and "subtractor" cells in a novel topology. The proposed multiplier features low-voltage operation, very low quiescent power consumption, high-linearity and high operating frequency. In comparison with a previously reported multiplier circuit, simulated results using a 0.35-mu m CMOS process show that, under the same static power consumption and supply voltage level of 1.2-V, the proposed circuit exhibits better linearity.
引用
收藏
页码：751 / +
页数：2
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