A 20GSps Track-and-Hold Circuit in 90nm CMOS Technology

被引：0

作者：

Kai, Tang ^{[1
]}

Qiao, Meng ^{[1
]}

机构：

[1] Southeast Univ, Inst RF & OE ICs, Nanjing, Jiangsu, Peoples R China

来源：

2012 INTERNATIONAL CONFERENCE ON ADVANCED TECHNOLOGIES FOR COMMUNICATIONS (ATC 2012) | 2012年

关键词：

5-BIT;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A low voltage, low power, high sampling rate open loop THA is proposed. The THA samples at 20GSps and combines three cascaded stages. The switch stage is implemented by the combination of CMOS switch and dummy switches to cancel the charge injection and clock feedthrough. The input and output stages are realized by the differential common-source amplifier with cross-couple pairs to improve the effects. Implemented in 90nm CMOS technology, the THA occupies 460 x 510 mu m(2) which includes I/O pads and takes the active area is only 85 x 95 mu m(2) with a power consumption of 47mW at a supply voltage of 1.2V. The THA delivers up to 32 dB spur-free-dynamic-range (SFDR) at nyquist sampling with 20GSps. The full scale input voltage is 0.6Vppd from 1.2V supply voltage.

引用

页码：237 / 240

页数：4

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