A 1-GHz, 56.3-dB SFDR CMOS track-and-hold circuit with body-bias control circuit

被引：4
|
作者：
Ohhata, Kenichi [1 ]
Yayama, Kosuke [1 ]
Shimizu, Yuichiro [1 ]
Yamashita, Kiichi [1 ]
机构：
[1] Kagoshima Univ, Kagoshima 8900065, Japan
来源：
IEICE ELECTRONICS EXPRESS | 2007年 / 4卷 / 22期
关键词：
track-and-hold circuit; distortion; body-bias effect;
D O I：
10.1587/elex.4.701
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper describes a high-speed CMOS track-and-hold (T/H) circuit with low distortion. We propose a T/H circuit with a body-bias control circuit to reduce distortion. This control circuit maintains a constant body bias for a switching MOS transistor in tracking mode. This reduces the variation in the threshold voltage due to the body-bias effect, thereby resulting in low distortion. The test chip fabricated using 90-nm CMOS technology shows a high SFDR of 56.3 dB at a sampling frequency of 1 GHz.
引用
收藏
页码：701 / 706
页数：6
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