A 6GHz Input Bandwidth Track-and-Hold circuit in HBT Technology

被引：0

作者：

Yang, Yujun ^{[1
]}

Li, Yao ^{[1
]}

Yu, Zhou ^{[2
]}

Zhang, Jun'an ^{[2
]}

Liu, Jun ^{[2
]}

Li, Jing ^{[1
]}

Fu, Dongbing ^{[1
]}

Chen, Guangbing ^{[2
]}

机构：

[1] CETC, Sichuan Inst Solid State Circuits, Chongqing 400060, Peoples R China

[2] Sci & Technol Analog Integrated Circuit Lab, Chongqing 400060, Peoples R China

来源：

PROCEEDINGS OF THE 2015 4TH NATIONAL CONFERENCE ON ELECTRICAL, ELECTRONICS AND COMPUTER ENGINEERING ( NCEECE 2015) | 2016年 / 47卷

关键词：

analog integrated circuits; analog to digital converter; heterojunction bipolar transistor; spurious-noise-free dynamic range; track and hold amplifier;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents the design of a 6GHz track-and hold circuit with input bandwidth. The track-and hold circuit adopts the design simulation of HBT process, able to work at a sampling frequency of 2 GHz, the highest sampling frequency can reach about 2 GHz. The SFDR of the track-and hold circuit can reach 64dB (simulation work at 2 GHz), The track-and hold circuit provides more than 66 dB hold -mode SFDR3 for 0 to 2GHz 1Vpp input signals at 2GHz. Early product parameters of the track-and hold circuit (working in 2 GHz sampling frequency) are as follows: the SFDR parameter can be achieved 64 dB.

引用

页码：1327 / 1332

页数：6

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