ROM-based direct digital synthesizer at 24 GHz clock frequency in InP DHBT technology

被引：22
|
作者：
Turner, Steven Eugene [1 ]
Chan, Richard T. [1 ]
Feng, Jeffrey T. [1 ]
机构：
[1] BAE Syst, Nashua, NH 03061 USA
来源：
IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS | 2008年 / 18卷 / 08期
关键词：
accumulator; digital to analog converter (DAC); direct digital synthesizer (DDS); emitter coupled logic (ECL); heterojunction bipolar transistor (HBT); high-speed integrated circuits; Indium Phosphide (InP); read-only memory (ROM);
D O I：
10.1109/LMWC.2008.2001025
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A direct digital synthesizer (DDS) implemented in InP double heterojunction bipolar transistor technology is reported. The DDS has a 12 b phase accumulator and a ROM-based phase converter. The DDS is capable of synthesizing output frequencies up to 12 GHz in steps that are 1/4096 of the 24 GHz clock rate. The worst case measured spurious free dynamic range (SFDR) is 30.7 dBc and the average SFDR over all frequency control words is 40.4 dBc. The DDS test circuit is implemented with 4470 transistors and it consumes 19.8 W of power.
引用
收藏
页码：566 / 568
页数：3
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