Compressed ROM high speed direct digital frequency synthesizer architecture

被引：0
|
作者：
Hai, U
Khan, MN
Imran, MS
Rehan, M
机构：
来源：
17th ICM 2005: 2005 International Conference on Microelectronics, Proceedings | 2005年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A low power, high speed direct digital frequency synthesizer (DDFS) is presented. Some approximations are used to avoid using a large ROM look-up table to store the sine values in a conventional DDFS. Significant saving in power consumption, due to the compressed ROM, renders the design more suitable for portable wireless communication applications. To demonstrate the proposed technique, a DDFS has been implemented using Taylor's series. The spurious free dynamic range is about 40 decibels at low synthesized frequencies.
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页码：36 / 39
页数：4
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