Implementation of Low Power Compressed ROM for Direct Digital Frequency Synthesizer

被引：0

作者：

Alkurwy, Salah Hasan ^{[1
]}

Ali, Sawal Hamid Md ^{[1
]}

Islam, Md. Shabiul ^{[2
]}

机构：

[1] Univ Kebangsaan Malaysia, Fac Engn & Built Environm, Dept Elect Elect & Syst Engn, Bangi 43600, Selangor, Malaysia

[2] Univ Kebangsaan Malaysia, Insitute Microengn & Nanoelect IMEN, Bangi 43600, Selangor, Malaysia

来源：

2014 IEEE INTERNATIONAL CONFERENCE ON SEMICONDUCTOR ELECTRONICS (ICSE) | 2014年

关键词：

direct digital frequency synthesizer (DDFS); ROM Look-up table (ROM LUT); phase accumulator (PA);

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A Low Power Compressed ROM Look-up table has been presented in this paper to achieve low power consumption of the direct digital frequency synthesizer as well small core size. The quarter wave symmetry technique is used to store only one quarter of the sine wave. The suggested 12-bit compressed ROM designed consists of three 4-bit sub-ROMs based on an angular decomposition technique and trigonometric identity. Exploiting the advantages of sine-cosine symmetrical attributes together with XOR logic gates, one sub-ROM block can be removed from the design. These techniques, compressed the ROM into 368 bits. The ROM compressed ratio is 534.2:1, with only two adders, two multipliers, and XOR-gates with high frequency resolution of 0.029 Hz.

引用

页码：309 / 312

页数：4

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