A 2-GHz Direct Digital Frequency Synthesizer Based on LUT and Rotation

被引：1

作者：

Yang, Yixiong ^{[1
]}

Wang, Zhibo ^{[1
]}

Yang, Pei ^{[1
]}

Chang, Meng-Fan ^{[2
]}

Ho, Mon-Shu ^{[3
]}

Yang, Huazhong ^{[1
]}

Liu, Yongpan ^{[1
]}

机构：

[1] Tsinghua Univ, Dept EE, Tsinghua Natl Lab Informat Sci & Technol TNList, Beijing, Peoples R China

[2] Natl Tsing Hua Univ, Dept Elect Engn, Hsinchu, Taiwan

[3] Natl Chung Hsin Univ, Dept Phys, Taichung, Taiwan

来源：

2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2018年

关键词：

Direct Digital Frequency Synthesizer (DDFS); LUT-ROT Architecture; Optimal Point;

D O I：

10.1109/ISCAS.2018.8351207

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper proposes a direct digital frequency synthesizer (DDFS) based on Lookup-Table-Rotation (LUT-ROT) architecture. The DDFS takes the advantages of coarse-fine LUT and pipelined rotation units to achieve both high-speed and high-resolution. Based on the analysis of approximation error, the trade-off between accuracy and memory usage is achieved, which leads to the lowest amplitude of noise and the smallest size of LUT. Experimental results show that the DDFS achieves 11.7mW/GHz power consumption and 96dBc SFDR in 2-GHz clock frequency.

引用

页数：5

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