A 2-V, 2-GHz low-power direct digital frequency synthesizer chip-set for wireless communication

被引:46
|
作者
Yamagishi, A [1 ]
Ishikawa, M
Tsukahara, T
Date, S
机构
[1] NTT, Wireless Syst Labs, Kanagawa 239, Japan
[2] NTT, Syst Elect Labs, Kanagawa 24301, Japan
[3] NTT, Human Interface Labs, Kanagawa 239, Japan
关键词
DDFS; digital-to-analog converter; direct digital frequency synthesizer; doubler; up-converter; wireless communication;
D O I
10.1109/4.658622
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A 2-GHz direct digital frequency synthesizer (DDFS) chip-set is presented which operates at a very low supply voltage of 2 V. The chip-set consists of a CMOS DDFS-large scale integrator (LSI) which synthesizes a sine wave at 55 Msps with an internal 10-b digital-to-analog converter (DAC) and Si-bipolar image-reject up-converters. To achieve both high purity and low power dissipation, we developed a distortion-free up-conversion architecture and an efficient ROM output bit-width reduction technique, Operation of 2-V for the entire chip-set becomes possible because of the use of both multithreshold-voltage CMOS in the D/A converters and current-folded double-balanced mixers in the microwave up-converters. The synthesizer achieves a wide spurious-free dynamic range of 50 dB and a low power dissipation of less than 160 mW at 2 GHz.
引用
收藏
页码:210 / 217
页数:8
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