Implementation of Chip-Level EMC Strategies in 0.18 μm CMOS Technology

被引：0

作者：

Chang, Yin-Cheng ^{[1
,2
]}

Wang, Ping-Yi ^{[1
]}

Hsu, Shawn S. H. ^{[1
]}

Yen, Mao-Hsu ^{[3
]}

Chang, Yen-Tang ^{[4
]}

Dong, Jian-Li ^{[4
]}

Lin, Ta-Yeh ^{[2
]}

Chang, Da-Chiang ^{[2
]}

机构：

[1] Natl Tsing Hua Univ, Inst Elect Engn, Hsinchu, Taiwan

[2] Natl Chip Implementat Ctr, Natl Appl Res Labs, Hsinchu, Taiwan

[3] Natl Taiwan Ocean Univ, Dept Comp Sci & Engn, Keelung, Taiwan

[4] Bur Stand Metrol & Inspect, MOEA, Taipei, Taiwan

来源：

2017 ASIA-PACIFIC INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (APEMC) | 2017年

关键词：

integrated circuit (IC); electromagnetic interference (EMI); electromagnetic susceptibility (EMS); slew rate controller; decoupling capacitor;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Two on-chip electromagnetic compatibility (EMC) solutions realized in the standard 0.18 mu m CMOS technology are proposed. A slew rate controller for electromagnetic interference (EMI) reduction is demonstrated by increasing the rise and fall time of signal to lower the harmonic energy on FFT spectrum. Besides, a MOS plus MOM decoupling capacitor for both EMI and electromagnetic susceptibility (EMS) issues is proposed to provide a 17.6 % added capacitance than the conventional decoupling capacitors under the same area. The experiment results prove that the proposed EMC strategies are effective and can be utilized in the chip design with low design complexity.

引用

页码：390 / 392

页数：3

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