共 50 条
- [1] Implementation of Chip-Level EMC Strategies in 0.18 μm CMOS Technology [J]. 2017 ASIA-PACIFIC INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (APEMC), 2017, : 390 - 392
- [3] Application of chip-level EMC in automotive product design [J]. 2006 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY, VOLS 1-3, PROCEEDINGS, 2006, : 842 - 848
- [4] An unique method to fabricate on-chip capacitors for chip-level EMC evaluation [J]. PROCEEDINGS OF THE 2013 20TH IEEE INTERNATIONAL SYMPOSIUM ON THE PHYSICAL & FAILURE ANALYSIS OF INTEGRATED CIRCUITS (IPFA 2013), 2013, : 366 - 369
- [5] Package and chip-level EMI/EMC structure design, modeling and simulation [J]. 49TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE - 1999 PROCEEDINGS, 1999, : 873 - 878
- [9] Efficient techniques for modeling chip-level interconnect, substrate and package parasitics [J]. DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION 1999, PROCEEDINGS, 1999, : 418 - 422
- [10] Chip-level MMSE equalization for high-speed synchronous CDMA in frequency selective multipath [J]. DIGITAL WIRELESS COMMUNICATION II, 2000, 4045 : 187 - 197