Implementation of 40Gbps PCS in 0.18μm CMOS Technology

被引：0

作者：

Lu, Jiafeng ^{[1
]}

Hu, Qingsheng ^{[1
]}

机构：

[1] Southeast Univ, Inst RF & OE ICs, Nanjing, Jiangsu, Peoples R China

来源：

INTERNATIONAL CONFERENCE ON REMOTE SENSING AND WIRELESS COMMUNICATIONS (RSWC 2014) | 2014年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a design of 40Gbps TX PCS compatible with the protocol of IEEE 802.3ba. To achieve high data rate, pipeline strategy is employed. Additionally, the working speed of the parallel scrambler is improved by dividing large XOR logic into some small ones and inserting registers between them. Dedicating design of block distribution and gearbox module reduces the area further. This design has been implemented in 0.18 mu m CMOS process, and the simulation results show that the data rate can be up to of 40Gbps under the working frequency of 625MHz.

引用

页码：207 / 213

页数：7

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