Extend force-directed scheduling for system-level synthesis in timeconstrained system-on-chip design

被引:0
|
作者
Wu, Q [1 ]
Bian, JA [1 ]
Li, RF [1 ]
Wang, YF [1 ]
Wang, HL [1 ]
Wang, W [1 ]
Xie, W [1 ]
机构
[1] Hunan Univ, Coll Comp & Commun, Changsha 410082, Peoples R China
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Scheduling time-constrained task graph to minimize resource requirement is a common and important problem in system-level synthesis (SLS) for system-on-chip (SoC) designs. Many algorithms have been proposed to address this issue. In this paper, an extended scheduling algorithm based on force-directed heuristic is presented, which adopts a notion of continuous time rather than a notion of discrete time in high-level synthesis (HLS). Polynomial arithmetic is employed to calculate the force function and its extremal points. Preliminary experimental results show the feasibility of the proposed algorithm.
引用
收藏
页码:174 / 180
页数:7
相关论文
共 50 条
  • [31] A Formal Approach to Incremental Converter Synthesis for System-on-Chip Design
    Sinha, Roopak
    Girault, Alain
    Goessler, Gregor
    Roop, Partha S.
    ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2014, 20 (01) : 1 - 30
  • [32] System-level communication modeling for network-on-chip synthesis
    Gerstlauer, Andreas
    Shin, Dongwan
    Domer, Rainer
    Gajski, Daniel D.
    ASP-DAC 2005: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2005, : 45 - 48
  • [33] Imaging system-on-chip: Design and applications
    El Gamal, A
    2003 IEEE LEOS ANNUAL MEETING CONFERENCE PROCEEDINGS, VOLS 1 AND 2, 2003, : 690 - 691
  • [34] Asynchronous techniques for system-on-chip design
    Martin, Alain J.
    Nystroem, Mika
    PROCEEDINGS OF THE IEEE, 2006, 94 (06) : 1089 - 1120
  • [35] SoCDAL: System-on-chip design accelerator
    Ahn, Yongjin
    Han, Keesung
    Lee, Ganghee
    Song, Hyunjik
    Yoo, Junhee
    Choi, Kiyoung
    Feng, Xingguang
    ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2008, 13 (01)
  • [36] Design of the TRIO system-on-chip for aerospace
    Kottaras, G
    Sarris, E
    Paschalidis, B
    Stamatopoulos, N
    Paschalidis, N
    IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS, 2004, 40 (03) : 862 - 878
  • [37] Testability issues of system-on-chip design
    Novak, F
    INFORMACIJE MIDEM-JOURNAL OF MICROELECTRONICS ELECTRONIC COMPONENTS AND MATERIALS, 2001, 31 (02): : 84 - 87
  • [38] System-on-chip design: Engineering or art
    Stamenkovic, Z.
    2006 25TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS, VOLS 1 AND 2, PROCEEDINGS, 2006, : 401 - 408
  • [39] System-on-chip design for a statistical decoder
    Wang, Liang-Hao
    Zhu, Zheng
    Luo, Kai
    Li, Bingbo
    Zhang, Ming
    ASICON 2007: 2007 7TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2007, : 966 - 969
  • [40] Dependable design technique for system-on-chip
    Kubalik, Pavel
    Kubatova, Hana
    JOURNAL OF SYSTEMS ARCHITECTURE, 2008, 54 (3-4) : 452 - 464