Parallel Pipelined FFT Architecture for Real Valued Signals using Radix-2

The pipelined architecture has gained popularity due to its ability to achieve high throughput and low hardware complexity, low power consumption. Thus, these architectures are widely used in many applications, mainly for the real-time applications. The fast Fourier transform (FFT) offers optimized design for the complex samples, i.e., complex valued FFT (CFFT) but not for the real input samples, i.e., real-valued FFT (RFFT). This paper presents the four parallel pipelined architecture (PPA) for the RFFT by using a canonical-signed-digit multiplier (CSDM) to optimize the area. The obtained results are compared with the pipelined architecture of author Salehi et al. [1] and is examined that the proposed architecture is efficient in area optimization.