VLSI Architecture for FFT using Radix-2 Butterfly of Complex Valued Data

The Discrete Fourier Transform (DFT) is an important technique in the field of Digital Signal Processing (DSP) and Telecommunications, especially for applications in Orthogonal Frequency Division Multiplexing (OFDM) systems. The Fast Fourier Transform (FFT) is an efficient algorithm to compute the DFT and its inverse. The FFT processor plays a key role in the field of communication systems such as Digital Video or Audio Broadcasting, Wireless LAN with Standards of IEEE 802.11, High Speed Digital Subscriber Lines etc. In this paper involves the implementation of a area efficient 8-point, 16-point, 32-point, 64-point and 128-point single path delay feedback (SDF) and folding technique using radix-2 DIT FFT algorithm. The proposed algorithms are used in radix-2 butterfly in all stage. The proposed algorithm is area efficient and consumed delay in previous algorithm. The all design are implementation vertex-2p device family Xilinx software.