A high-performance architecture for EBCOT in the JPEG 2000 encoder

被引：2

作者：

Pastuszak, G ^{[1
]}

机构：

[1] Warsaw Univ Technol, Inst Radioelect, Warsaw, Poland

来源：

2005 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS - DESIGN AND IMPLEMENTATION (SIPS) | 2005年

关键词：

D O I：

10.1109/SIPS.2005.1579954

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

The architecture for EBCOT in JPEG 2000 is presented. The architecture embeds all functions necessary to produce the final codestream consistent with the JPEG 2000 specification. A number of hardware optimisation methods are used to achieve the high throughput at relatively low cost of hardware resources. The architecture is verified in simulations and synthesized for ASIC and FPGA technologies. Implementation results for FPGA Stratix II devices show that it can work at 120 MHz and process about 40 million samples per second in the regular lossless mode.

引用

页码：693 / 698

页数：6

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