High density and fully compatible embedded DRAM cell with 45nm MOS technology (CMOS6)

被引:0
|
作者
Sanuki, T [1 ]
Sogo, Y [1 ]
Oishi, A [1 ]
Okayama, Y [1 ]
Hasumi, R [1 ]
Morimasa, Y [1 ]
Kinoshita, T [1 ]
Komoda, T [1 ]
Tanaka, H [1 ]
Hiyama, K [1 ]
Komoguchi, T [1 ]
Matsumoto, T [1 ]
Oota, K [1 ]
Yokoyama, T [1 ]
Fukasaku, K [1 ]
Katsumata, R [1 ]
Kido, M [1 ]
Tamura, M [1 ]
Takegawa, Y [1 ]
Yoshimura, H [1 ]
Kasai, K [1 ]
Ohno, K [1 ]
Saito, M [1 ]
Aochi, H [1 ]
Iwai, M [1 ]
Nagashima, N [1 ]
Matsuoka, E [1 ]
Okamoto, Y [1 ]
Noguchi, T [1 ]
机构
[1] Toshiba Co Ltd, Syst LSI Div, SoC Res & Dev Ctr, Semicond Co,Isogo Ku, Yokohama, Kanagawa 2358522, Japan
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
For the first time, a deep trench based embedded DRAM cell for 45nm node system on a chip (SoC) applications is presented. We achieve both high data retention time and full compatibility with logic process, while scaling eDRAM cell down to 0.069 mu m(2) size. In order to compensate the loss of capacitance in aggressively scaled deep trench, high enhancement of storage node capacitance up to 60% is achieved by introducing the bottle etching process with LOCOS collar structure and the high-k node dielectric material (Al2O3). Hybrid STI structure is applied for void free gap filling, and high improvement of retention time is obtained by reduction of induced stress. Ultra Shallow Buried Strap (USBS) structure without silicide block process realizes the integration without any extra process after deep trench formation and extremely low strap resistance. No degradation of retention characteristics is observed by introducing Ni silicide on the top of storage node junction. Disposable sidewall spacer and Flash Lamp Anneal, which are key technologies of logic transistor, are also applied to eDRAM cell successfully. In addition, high functional test yield up to 61% has been obtained for 256Kb ADM.
引用
收藏
页码:14 / 15
页数:2
相关论文
共 50 条
  • [31] Fully differential Ultra-wideband LNA-Mixer for K to Ka Band receiver in 45nm CMOS SOI technology
    Wang, Yu
    Cui, Jie
    Zhang, Renli
    Sheng, Weixing
    PROCEEDINGS OF THE 2019 IEEE ASIA-PACIFIC MICROWAVE CONFERENCE (APMC), 2019, : 16 - 18
  • [32] A Study of Self-Aligned Nitride Erasable OTP Cell by 45-nm CMOS Fully Compatible Process
    Huang, Chia-En
    Chen, Ying-Je
    Lai, Han-Chao
    King, Ya-Chin
    Lin, Chrong Jung
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2009, 56 (06) : 1228 - 1234
  • [33] Low Power High Speed 1-bit Full Adder Circuit design at 45nm CMOS Technology
    Yadav, Ashish Kumar
    Shrivatava, Bhavana P.
    Dadoriya, Ajay Kumar
    2017 INTERNATIONAL CONFERENCE ON RECENT INNOVATIONS IN SIGNAL PROCESSING AND EMBEDDED SYSTEMS (RISE), 2017, : 427 - 432
  • [34] High density and high speed SRAM bit-cells and ring oscillators due to laser annealing for 45nm bulk CMOS
    Pouydebasque, A
    Dumont, B
    Denorme, S
    Wacquant, F
    Bidaud, M
    Laviron, C
    Halimaoui, A
    Chaton, C
    Chapon, JD
    Gouraud, P
    Leverd, F
    Bernard, H
    Warrick, S
    Delille, D
    Romanjek, K
    Gwoziecki, R
    Planes, N
    Vadot, S
    Pouilloux, I
    Arnaud, F
    Boeuf, F
    Skotnicki, T
    IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2005, TECHNICAL DIGEST, 2005, : 679 - 682
  • [35] A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors
    Ghani, T
    Armstrong, M
    Auth, C
    Bost, M
    Charvat, P
    Glass, G
    Hoffmann, T
    Johnson, K
    Kenyon, C
    Klaus, J
    McIntyre, B
    Mistry, K
    Murthy, A
    Sandford, J
    Silberstein, M
    Sivakumar, S
    Smith, P
    Zawadzki, K
    Thompson, S
    Bohr, M
    2003 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST, 2003, : 978 - 980
  • [36] Fully Depleted Double-Gate 1T-DRAM Cell with NVM Function for High Performance and High Density Embedded DRAM
    Park, Ki-Heung
    Kim, Young Min
    Kwon, Hyuck-In
    Kong, Seong Ho
    Lee, Jong-Ho
    2009 IEEE INTERNATIONAL MEMORY WORKSHOP, 2009, : 32 - +
  • [37] Proposal of a logic compatible merged-type gain cell for high-density embedded DRAM's
    Mukai, M
    Hayashi, Y
    Komatsu, Y
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 1999, 46 (06) : 1201 - 1206
  • [38] Leakage Current Optimization in 9T SRAM Bit-cell with Sleep Transistor at 45nm CMOS Technology
    Ruhil, Shaifali
    Shukla, Neeraj Kr.
    2017 INTERNATIONAL CONFERENCE ON COMPUTING AND COMMUNICATION TECHNOLOGIES FOR SMART NATION (IC3TSN), 2017, : 259 - 261
  • [39] 45nm high-k/metal-gate CMOS technology for GPU/NPU applications with highest PFET performance
    Huang, H. T.
    Liu, Y. C.
    Hou, Y. T.
    Chen, R. C-J
    Lee, C. H.
    Chao, Y. S.
    Hsu, P. F.
    Chen, C. L.
    Guo, W. H.
    Yang, W. C.
    Perng, T. H.
    Shen, J. J.
    Yasuda, Y.
    Goto, K.
    Chen, C. C.
    Huang, K. T.
    Chuang, H.
    Diaz, C. H.
    Liang, M. S.
    2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2, 2007, : 285 - 288
  • [40] 45nm CMOS - Silicon Photonics Monolithic Technology (45CLO) for next-generation, low power and high speed optical interconnects
    Rakowski, Michal
    Meagher, Colleen
    Nummy, Karen
    Aboketaf, Abdelsalam
    Ayala, Javier
    Bian, Yusheng
    Harris, Brendan
    Mclean, Kate
    McStay, Kevin
    Sahin, Asli
    Medina, Louis
    Peng, Bo
    Sowinski, Zoey
    Stricker, Andy
    Houghton, Thomas
    Hedges, Crystal
    Giewont, Ken
    Jacob, Ajey
    Letavic, Ted
    Riggs, Dave
    Yu, Anthony
    Pellerin, John
    2020 OPTICAL FIBER COMMUNICATIONS CONFERENCE AND EXPOSITION (OFC), 2020,