High density and fully compatible embedded DRAM cell with 45nm MOS technology (CMOS6)

被引:0
|
作者
Sanuki, T [1 ]
Sogo, Y [1 ]
Oishi, A [1 ]
Okayama, Y [1 ]
Hasumi, R [1 ]
Morimasa, Y [1 ]
Kinoshita, T [1 ]
Komoda, T [1 ]
Tanaka, H [1 ]
Hiyama, K [1 ]
Komoguchi, T [1 ]
Matsumoto, T [1 ]
Oota, K [1 ]
Yokoyama, T [1 ]
Fukasaku, K [1 ]
Katsumata, R [1 ]
Kido, M [1 ]
Tamura, M [1 ]
Takegawa, Y [1 ]
Yoshimura, H [1 ]
Kasai, K [1 ]
Ohno, K [1 ]
Saito, M [1 ]
Aochi, H [1 ]
Iwai, M [1 ]
Nagashima, N [1 ]
Matsuoka, E [1 ]
Okamoto, Y [1 ]
Noguchi, T [1 ]
机构
[1] Toshiba Co Ltd, Syst LSI Div, SoC Res & Dev Ctr, Semicond Co,Isogo Ku, Yokohama, Kanagawa 2358522, Japan
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
For the first time, a deep trench based embedded DRAM cell for 45nm node system on a chip (SoC) applications is presented. We achieve both high data retention time and full compatibility with logic process, while scaling eDRAM cell down to 0.069 mu m(2) size. In order to compensate the loss of capacitance in aggressively scaled deep trench, high enhancement of storage node capacitance up to 60% is achieved by introducing the bottle etching process with LOCOS collar structure and the high-k node dielectric material (Al2O3). Hybrid STI structure is applied for void free gap filling, and high improvement of retention time is obtained by reduction of induced stress. Ultra Shallow Buried Strap (USBS) structure without silicide block process realizes the integration without any extra process after deep trench formation and extremely low strap resistance. No degradation of retention characteristics is observed by introducing Ni silicide on the top of storage node junction. Disposable sidewall spacer and Flash Lamp Anneal, which are key technologies of logic transistor, are also applied to eDRAM cell successfully. In addition, high functional test yield up to 61% has been obtained for 256Kb ADM.
引用
收藏
页码:14 / 15
页数:2
相关论文
共 50 条
  • [11] A Floating Body Cell (FBC) fully compatible with 90nm CMOS Technology Node for Embedded Applications
    Hamamoto, Takeshi
    Minami, Yoshihiro
    Shino, Tomoaki
    Sakamoto, Atsushi
    Higashi, Tomoki
    Kusunoki, Naoki
    Fujita, Katsuyuki
    Hatsuda, Kosuke
    Ohsawa, Takashi
    Aoki, Nobutoshi
    Tanimoto, Hiroyoshi
    Morikado, Mutsuo
    Nakajima, Hiroomi
    Inoh, Kazumi
    Nitayama, Akihiro
    2006 IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUIT DESIGN AND TECHNOLOGY, PROCEEDINGS, 2006, : 30 - +
  • [12] A Floating Body Cell (FBC) fully compatible with 90nm CMOS Technology(CMOS IV) for 128Mb SOI DRAM
    Minami, Y
    Shino, T
    Sakamoto, A
    Higashi, T
    Kusunoki, N
    Fujita, K
    Hatsuda, K
    Ohsawa, T
    Aoki, N
    Tanimoto, H
    Morikado, M
    Nakajima, H
    Inoh, K
    Hamamoto, T
    Nitayama, A
    IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2005, TECHNICAL DIGEST, 2005, : 317 - 320
  • [13] High-activation laser anneal process for the 45nm CMOS technology platform
    Bidaud, M.
    Bono, H.
    Chaton, C.
    Dumont, B.
    Huard, V.
    Morin, P.
    Proencamota, L.
    Ranica, R.
    Ribes, G.
    15TH IEEE INTERNATIONAL CONFERENCE ON ADVANCED THERMAL PROCESSING OF SEMICONDUCTORS - RTP 2007, 2007, : 251 - +
  • [14] A 0.65V Embedded SDRAM with Smart Boosting and Power Management in a 45nm CMOS Technology
    Pyo, Suk-Soo
    Kim, Jun-Sung
    Kim, Jung-Han
    Jung, Hyun-Taek
    Song, Tae-Joong
    Lee, Cheol-Ha
    Kim, Gyu-Hong
    Lee, Young-Keun
    Kim, Kee-Sup
    2012 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2012,
  • [15] High performance transistors featured in an aggressively scaled 45nm bulk CMOS technology
    Luo, Z.
    Rovedo, N.
    Ong, S.
    Phoong, B.
    Eller, M.
    Utomo, H.
    Ryou, C.
    Wang, H.
    Stierstorfer, R.
    Clevenger, L.
    Kim, S.
    Toomey, J.
    Sciacca, D.
    Li, J.
    Wille, W.
    Zhaol, L.
    Teo, L.
    Dyer, T.
    Fang, S.
    Yan, J.
    Kwon, O.
    Kwon, O.
    Park, D.
    Holt, J.
    Han, J.
    Chan, V.
    Yuan, J.
    Kebede, T.
    Lee, H.
    Kim, S.
    Lee, S.
    Vayshenker, A.
    Yang, Z.
    Tian, C.
    Ng, H.
    Shang, H.
    Hierlemann, M.
    Ku, J.
    Sudijonol, J.
    Ieong, M.
    2007 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2007, : 16 - +
  • [16] Power analysis of 3T DRAM Cell using FinFET at 45nm Process Technology
    Mudgal, Ambrish
    Akashe, Shyam
    Singh, Shyam Babu
    PROCEEDINGS OF THE 2012 WORLD CONGRESS ON INFORMATION AND COMMUNICATION TECHNOLOGIES, 2012, : 555 - 560
  • [17] A Fully-integrated Ka-band Stacked Power Amplifier in 45nm CMOS SOI Technology
    Chen, Jing-Hwa
    Helmi, Sultan R.
    Mohammadi, Saeed
    2013 IEEE 13TH TOPICAL MEETING ON SILICON MONOLITHIC INTEGRATED CIRCUITS IN RF SYSTEMS (SIRF), 2013, : 75 - 77
  • [18] eSiGe global and micro loading effect study in high performance 45nm CMOS technology
    He, Yonggen
    Tu, Huojin
    Lin, Jing
    Song, Hualong
    Wang, Jun
    Ma, Guiyin
    Xu, Weizhong
    Ye, Bin
    Yu, Tzuchiang
    Wu, Jingang
    CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE 2011 (CSTIC 2011), 2011, 34 (01): : 731 - 736
  • [19] A Low Voltage 6T SRAM Cell Design and Analysis Using Cadence 90nm And 45nm CMOS Technology
    Kalpana, T.
    Reddy, Challa Lakshmi
    Saranya, Bandaru
    Naveen, Poluboyina
    2024 7TH INTERNATIONAL CONFERENCE ON DEVICES, CIRCUITS AND SYSTEMS, ICDCS 2024, 2024, : 188 - 194
  • [20] 45-nm silicon-on-insulator CMOS technology integrating embedded DRAM for high-performance server and ASIC applications
    Iyer, S. S.
    Freeman, G.
    Brodsky, C.
    Chou, A. I.
    Corliss, D.
    Jain, S. H.
    Lustig, N.
    McGahay, V.
    Narasimha, S.
    Norum, J.
    Nummy, K. A.
    Parries, P.
    Sankaran, S.
    Sheraw, C. D.
    Varanasi, P. R.
    Wang, G.
    Weybright, M. E.
    Yu, X.
    Crabbe, E.
    Agnello, P.
    IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 2011, 55 (03)