Partially detectable faults in synchronous sequential circuits

被引：0
|
作者：
Dawoud, DS
机构：
来源：
AFRICON '96 - 1996 IEEE AFRICON : 4TH AFRICON CONFERENCE IN AFRICA, VOLS I & II: ELECTRICAL ENERGY TECHNOLOGY; COMMUNICATION SYSTEMS; HUMAN RESOURCES | 1996年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Faults in sequential circuits are studied. Undetectable and redundant faults under different modes of operation are analysed. Undetectable faults are split into two classes: operationally redundant faults and partially redundant faults. Operationally redundant faults are defined as faults that are never manifested as faulty output during normal operation. Partially redundant faults are defined as faults that can affect the output sequence under certain initial conditions otherwise it is undetectable. Faults in sequential circuits are, accordingly, classified into three classes: detectable, partially detectable and operationally redundant. Test generation strategies and the relation between test sequences under different modes of operation are analysed.
引用
收藏
页码：795 / 800
页数：6
相关论文
共 50 条
  • [31] Hierarchical identification of untestable faults in sequential circuits
    Raik, Jaan
    Ubar, Raimund
    Krivenko, Anna
    Kruus, Margus
    [J]. DSD 2007: 10TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN ARCHITECTURES, METHODS AND TOOLS, PROCEEDINGS, 2007, : 668 - 671
  • [32] DESIGN OF DIAGNOSTIC TESTS FOR SYNCHRONOUS SEQUENTIAL CIRCUITS
    TYURIN, AV
    [J]. AUTOMATION AND REMOTE CONTROL, 1974, 35 (07) : 1132 - 1140
  • [33] RECONVERGENCE PHENOMENON IN SYNCHRONOUS SEQUENTIAL-CIRCUITS
    NANDA, NK
    BENNETTS, RG
    [J]. ELECTRONICS LETTERS, 1980, 16 (08) : 303 - 304
  • [34] Oscillation and Transition Tests for Synchronous Sequential Circuits
    Li, Katherine Shu-Min
    [J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2013, 21 (12) : 2338 - 2343
  • [35] Diagnostic fault simulation for synchronous sequential circuits
    Chen, SC
    Jou, JM
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1997, 16 (03) : 299 - 308
  • [36] Preprocessing techniques of ATPG for synchronous sequential circuits
    Xu, CP
    Zhi, L
    Wei, M
    [J]. ICEMI'2003: PROCEEDINGS OF THE SIXTH INTERNATIONAL CONFERENCE ON ELECTRONIC MEASUREMENT & INSTRUMENTS, VOLS 1-3, 2003, : 238 - 242
  • [37] Functional test generation for synchronous sequential circuits
    Srinivas, MK
    Jacob, J
    Agrawal, VD
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1996, 15 (07) : 831 - 843
  • [38] ANALYSIS OF SYNCHRONOUS GENERATOR SEQUENTIAL SHORT CIRCUITS
    SRIHARAN, S
    DEOLIVEIRA, SEM
    [J]. PROCEEDINGS OF THE INSTITUTION OF ELECTRICAL ENGINEERS-LONDON, 1977, 124 (06): : 549 - 553
  • [39] A STUDY OF THE RESETABILITY OF SYNCHRONOUS SEQUENTIAL-CIRCUITS
    LIOY, A
    PONCINO, M
    [J]. MICROPROCESSING AND MICROPROGRAMMING, 1993, 38 (1-5): : 395 - 402
  • [40] OPTIMUM STATE ASSIGNMENT FOR SYNCHRONOUS SEQUENTIAL CIRCUITS
    STORY, JR
    HARRISON, HJ
    REINHARD, EA
    [J]. IEEE TRANSACTIONS ON COMPUTERS, 1972, C 21 (12) : 1365 - 1373
12345