共 50 条
- [1] MIRA: A multi-layered on-chip interconnect router architecture [J]. ISCA 2008 PROCEEDINGS: 35TH INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE, 2008, : 251 - 261
- [3] A High Performance Router With Dynamic Buffer Allocation For On-Chip Interconnect Networks [J]. 2010 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, 2010, : 462 - 467
- [4] A High-throughpur Low-latency Router for On-chip Interconnect Networks [J]. Hunan Daxue Xuebao/Journal of Hunan University Natural Sciences, 2023, 50 (08): : 141 - 146
- [6] Design and Analysis of On-Chip Router [J]. 2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1-4, 2008, : 1827 - 1830
- [7] Configurable network-on-chip router macrocells [J]. MICROPROCESSORS AND MICROSYSTEMS, 2016, 45 : 141 - 150
- [8] Four-port mode-selective silicon optical router for on-chip optical interconnect [J]. OPTICS EXPRESS, 2018, 26 (08): : 9740 - 9748
- [9] A virtual channel router for on-chip networks [J]. IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS, 2004, : 289 - 293
- [10] Extraction and applications of on-chip interconnect inductance [J]. 2004: 7TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUITS TECHNOLOGY, VOLS 1- 3, PROCEEDINGS, 2004, : 142 - 146