TrafficLite: A Configurable On-Chip Interconnect Router Microarchitecture

被引：0

作者：

Xie Bin ^{[1
]}

Fu Weiwei ^{[1
]}

Chen Tian-zhou ^{[1
]}

机构：

[1] Zhejiang Univ, Coll Comp Sci, Hangzhou 310003, Zhejiang, Peoples R China

来源：

2012 IEEE 14TH INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING AND COMMUNICATIONS & 2012 IEEE 9TH INTERNATIONAL CONFERENCE ON EMBEDDED SOFTWARE AND SYSTEMS (HPCC-ICESS) | 2012年

关键词：

network-on-chip; router architecture; pre-configuration; communication latency; power consumption; MODEL;

D O I：

10.1109/HPCC.2012.74

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

Network-on-chip (NoC) has become a candidate communication infrastructure in Chip Multiprocessor. Study shows the resource utilization is quite low in on-chip network. In this paper, TrafficLite router is proposed to shut down the less used switch in the router. In the TrafficLite router, there are data paths to bypass the switch. Injection and ejection ports are separated from other ports in order to inject and eject packet when the router is set to lite mode. And the managements of virtual channels and buffers are also adjusted to fulfill the requirements of the turn free transmission. Furthermore, an enhanced XY routing algorithm is introduced to avoid the ping-pong transmission in the network. Both synthetic traffic and real world applications show the advantage of TrafficLite router. Up to 30% reduction of latency and 60% reduction of power consumption can be gained.

引用

页码：501 / 508

页数：8

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