Anti-PVT-Variation Low-Power Time-to-Digital Converter Design Using 90-nm CMOS Process

被引：11

作者：

Wang, Chua-Chin ^{[1
,2
]}

Chao, Kuan-Yu ^{[1
]}

Sampath, Sivaperumal ^{[3
]}

Suresh, Ponnan ^{[3
]}

机构：

[1] Natl Sun Yat Sen Univ, Dept Elect Engn, Kaohsiung 80424, Taiwan

[2] Natl Sun Yat Sen Univ, Inst Undersea Technol, Kaohsiung 80424, Taiwan

[3] Vel Tech, Dept Elect & Commun Engn, Chennai 600054, Tamil Nadu, India

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2020年 / 28卷 / 09期

关键词：

Delays; Detectors; Image edge detection; Very large scale integration; Temperature measurement; Feature extraction; D flip-flip (DFF); process voltage and temperature (PVT); PVT corner detector; synchronization; time-to-digital converter (TDC); ADC;

D O I：

10.1109/TVLSI.2020.3008424

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

One of the most important functional units in digital circuitry for synchronization and measurement is time-to-digital converter (TDC) which always requires higher resolution and accuracy. In this brief, a process, voltage, temperature (PVT)-variation-insensitive TDC featured with a PVT detector is proposed. The PVT detector takes advantage of another delay line with optimized locking conditions to differentiate PVT corners. The proposed TDC is physically realized using a 90-nm CMOS process. On-silicon measurement results demonstrate 30-ps resolution, < 1.5 LSB INL/DNL, and 2.22 mW at 100 MHz and 1.2-V supply voltage.

引用

页码：2069 / 2073

页数：5

共 50 条

[31] A Low-Power 2.4-GHz CMOS GFSK Transceiver With a Digital Demodulator Using Time-to-Digital Conversion
Chen, Chia-Pei
Yang, Ming-Jen
Huang, Hsun-Hsiu
Chiang, Tung-Ying
Chen, Jheng-Liang
Chen, Ming-Chieh
Wen, Kuei-Ann
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2009, 56 (12) : 2738 - 2748
[32] Low-power successive approximation converter with 0.5 V supply in 90 nm CMOS
Gambini, Simone
Rabaey, Jan
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2007, 42 (11) : 2348 - 2356
[33] Low-Power 3rd order ΣΔ Modulator in CMOS 90-nm for sensor interface applications
Giuffredi, Luca
Pietrini, Giorgio
Ronchi, Marco
Magnanini, Alessandro
Boni, Andrea
2015 IEEE 13TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS), 2015,
[34] A 90nm CMOS Digital PLL Based on Vernier-Gated-Ring-Oscillator Time-to-Digital Converter
Lu, Ping
Wu, Ying
Andreani, Pietro
2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012), 2012, : 2593 - 2596
[35] Low-Power Low-Cost Direct Digital Frequency Synthesizer Using 90 nm CMOS Technology
Ellaithy, Dina M.
JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2022, 31 (11)
[36] Highly accurate cyclic CMOS time-to-digital converter with extremely low power consumption
Chen, PK
Liu, SI
Wu, JH
ELECTRONICS LETTERS, 1997, 33 (10) : 858 - 860
[37] A Low-Power Analog-to-Digital Converter for Multi-Gigabit Wireless Receiver in 90nm CMOS
Chuang, Kevin
Yeh, David
Pinel, Stephane
Laskar, Joy
2010 EUROPEAN MICROWAVE INTEGRATED CIRCUITS CONFERENCE (EUMIC), 2010, : 218 - 221
[38] A Digital-to-Time Converter with Coupled Phase-Rotating LC Oscillators in 90-nm CMOS Technology
Wu, Ming-Ting
Hsu, Hao-Che
Hsieh, Ping-Hsuan
2019 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2019,
[39] Low-power Time-to-Digital Converter based on Vernier Gated-Ring-Oscillator
Bayat, Samaneh
Rezaee-Dehsorkh, Hamidreza
Ravanshad, Nassim
26TH IRANIAN CONFERENCE ON ELECTRICAL ENGINEERING (ICEE 2018), 2018, : 1441 - 1445
[40] A LOW POWER VERNIER TIME-TO-DIGITAL CONVERTER USING ADIABATIC LOGIC
Mahima, R.
Muralidharan, D.
2017 INTERNATIONAL CONFERENCE ON NETWORKS & ADVANCES IN COMPUTATIONAL TECHNOLOGIES (NETACT), 2017, : 90 - 94

← 1 2 3 4 5 →