Anti-PVT-Variation Low-Power Time-to-Digital Converter Design Using 90-nm CMOS Process

被引：11

作者：

Wang, Chua-Chin ^{[1
,2
]}

Chao, Kuan-Yu ^{[1
]}

Sampath, Sivaperumal ^{[3
]}

Suresh, Ponnan ^{[3
]}

机构：

[1] Natl Sun Yat Sen Univ, Dept Elect Engn, Kaohsiung 80424, Taiwan

[2] Natl Sun Yat Sen Univ, Inst Undersea Technol, Kaohsiung 80424, Taiwan

[3] Vel Tech, Dept Elect & Commun Engn, Chennai 600054, Tamil Nadu, India

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2020年 / 28卷 / 09期

关键词：

Delays; Detectors; Image edge detection; Very large scale integration; Temperature measurement; Feature extraction; D flip-flip (DFF); process voltage and temperature (PVT); PVT corner detector; synchronization; time-to-digital converter (TDC); ADC;

D O I：

10.1109/TVLSI.2020.3008424

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

One of the most important functional units in digital circuitry for synchronization and measurement is time-to-digital converter (TDC) which always requires higher resolution and accuracy. In this brief, a process, voltage, temperature (PVT)-variation-insensitive TDC featured with a PVT detector is proposed. The PVT detector takes advantage of another delay line with optimized locking conditions to differentiate PVT corners. The proposed TDC is physically realized using a 90-nm CMOS process. On-silicon measurement results demonstrate 30-ps resolution, < 1.5 LSB INL/DNL, and 2.22 mW at 100 MHz and 1.2-V supply voltage.

引用

页码：2069 / 2073

页数：5

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